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1 ltc1736 5-bit adjustable high efficiency synchronous step-down switching regulator figure 1. high efficiency step-down converter n dual n-channel mosfet synchronous drive n synchronizable/programmable fixed frequency n wide v in range: 3.5v to 36v operation n 5-bit digital-to-analog v out selection: 0.925v to 2.00v range with 50mv/25mv steps n opti-loop tm compensation minimizes c out n 1% output voltage accuracy n power good output voltage monitor n active voltage positioning compatible n output overvoltage crowbar protection n internal current foldback n latched short-circuit shutdown timer with defeat option n forced continuous control pin n optional programmable soft-start n remote output voltage sense n available in 24-lead ssop package n notebook and palmtop computers, pdas n power supply for mobile pentium ? ii and pentium iii processors n low voltage power supplies the ltc ? 1736 is a synchronous step-down switching regulator controller optimized for cpu power. the output voltage is programmed by a 5-bit digital-to-analog con- verter (dac) that adjusts the output voltage from 0.925v to 2.00v according to intel mobile vid specifications. the 0.8v reference is compatible with future microprocessor generations. the operating frequency (synchronizable up to 500khz) is set by an external capacitor allowing maximum flexibility in optimizing efficiency. the output voltage is monitored by a power good window comparator that indicates when the output is within 7.5% of its programmed value. protection features include: internal foldback current lim- iting, output overvoltage crowbar and optional short-cir- cuit shutdown. soft-start is provided by an external capaci- tor that can be used to properly sequence supplies. the operating current level is user-programmable via an exter- nal current sense resistor. wide input supply range allows operation from 3.5v to 30v (36v maximum). pin defeatable burst mode tm operation provides high effi- ciency at low load currents. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. , ltc and lt are registered trademarks of linear technology corporation. opti-loop and burst mode are trademarks of linear technology corporation. pentium is a registered trademark of intel corporation. v osense i th 47pf c c1 330pf c b 0.22 f d b cmdsh-3 v in 5v to 24v c osc 47pf run/ss pgnd bg 1000pf boost sw vidv cc intv cc 4.7 f m2 fds6680a 2 m1 fds6680a c out : panasonic eefueog181r c in : marcon thcr70eih226zt l1: panasonic etqp6rzir20hfa r sense : irc lrf2010-01-r004j d1 mbrs340t3 1736 f01 c ss 0.1 f c c2 47pf c osc r c 33k r sense 0.004 pgood vid4 vid3 vid2 vid1 vid0 sgnd sense ltc1736 sense + tg v in + c out 180 f/4v 4 c in 22 f/50v 2 ceramic v out 1.35v to 1.60v 12a + l1 1.2 h features descriptio u applicatio s u typical applicatio u
2 ltc1736 absolute axi u rati gs w ww u package/order i for atio uu w (note 1) input supply voltage (v in ).........................36v to C 0.3v topside driver supply voltage (boost)....42v to C 0.3v switch voltage (sw) ....................................36v to C 5v extv cc , vidv cc , (boost C sw) voltages .. 7v to C 0.3v sense + , sense C .......................... 1.1(intv cc ) to C 0.3v fcb voltage ............................(intv cc + 0.3v) to C 0.3v i th , v osense , v fb voltage .........................2.7v to C 0.3v run/ss, vid0 to vid4, pgood voltages ....7v to C 0.3v peak driver output current <10 m s (tg, bg) .............. 3a intv cc output current ......................................... 50ma operating ambient temperature range LTC1736C ............................................... 0 c to 85 c ltc1736i ............................................ C 40 c to 85 c junction temperature (note 2) ............................. 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number consult factory for military grade parts. t jmax = 125 c, q ja = 110 c/w 1 2 3 4 5 6 7 8 9 10 11 12 top view g package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 c osc run/ss i th fcb sgnd pgood sense sense + v fb v osense vid0 vid1 tg boost sw v in intv cc bg pgnd extv cc vidv cc vid4 vid3 vid2 electrical characteristics LTC1736Cg ltc1736ig the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss = 5v unless otherwise noted. symbol parameter conditions min typ max units main control loop v osense output voltage set accuracy (note 3) see table 1 l 1% d v linereg reference voltage line regulation v in = 3.6v to 30v (note 3) 0.001 0.02 %/v d v loadreg output voltage load regulation (note 3) measured in servo loop; v ith = 0.7v l 0.1 0.3 % measured in servo loop; v ith = 2v l C 0.1 C 0.3 % g m transconductance amplifier g m 1.3 mmho v fcb forced continuous threshold l 0.76 0.8 0.84 v i fcb forced continuous current v fcb = 0.85v C 0.17 C 0.3 m a v ovl feedback overvoltage lockout l 0.84 0.86 0.88 v i q input dc supply current (note 4) normal mode 450 m a shutdown v run/ss = 0v 15 25 m a v run/ss run pin start threshold v run/ss , ramping positive 1.0 1.5 1.9 v v run/ss run pin begin latchoff threshold v run/ss , ramping positive 4.1 4.5 v i run/ss soft-start charge current v run/ss = 0v C 0.7 C 1.2 m a i scl run/ss discharge current soft short condition, v fb = 0.5v, 0.5 2 4 m a v run/ss = 4.5v uvlo undervoltage lockout measured at v in pin (v in ramping down) l 3.5 3.9 v d v sense(max) maximum current sense threshold v fb = 0.7v l 60 75 85 mv i sense sense pins total source current v sense C = v sense + = 0.8v 60 80 m a t on(min) minimum on-time tested with a square wave (note 8) 160 200 ns tg transition time: (note 9) tg t r rise time c load = 3300pf 50 90 ns tg t f fall time c load = 3300pf 50 90 ns
3 ltc1736 electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss = 5v unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: LTC1736Cg, ltc1736ig: t j = t a + (p d ? 110 c/w) note 3: the ltc1736 is tested in a feedback loop that servos v fb to the balance point for the error amplifier (v ith = 1.2v). note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 5: oscillator frequency is tested by measuring the c osc charge current (i osc ) and applying the formula: note 6: with all five vid inputs floating (or tied to vidv cc ) the vidv cc current is typically < 1 m a. however, the vidv cc current will rise and be approximately equal to the number of grounded vid input pins times (vidv cc C 0.6v)/40k. (see the applications information section for more detail.) note 7: each built-in pull-up resistor attached to the vid inputs also has a series diode to allow input voltages higher than the vidv cc supply without damage or clamping. (see the applications information section for more detail.) note 8: the minimum on-time condition corresponds to the on inductor peak-to-peak ripple current 3 40% of i max (see minimum on-time considerations in the applications information section). note 9: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. f cpf i i osc osc chg dis = + ? ? ? ? + ? ? ? ? 8 477 10 11 11 11 1 .( ) () symbol parameter conditions min typ max units bg transition time: (note 9) bg t r rise time c load = 3300pf 50 90 ns bg t f fall time c load = 3300pf 40 80 ns tg/bg t1d top gate off to synchronous c load = 3300pf each driver 100 ns gate-on delay time tg/bg t2d synchronous gate off to top c load = 3300pf each driver 70 ns gate-on delay time internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v 5.0 5.2 5.4 v v ldo(int) internal v cc load regulation i cc = 0ma to 20ma, v extvcc = 4v 0.2 1 % v ldo(ext) extv cc drop voltage i cc = 20ma, v extvcc = 5v 130 200 mv v extvcc extv cc switchover voltage i cc = 20ma, extv cc ramping positive l 4.5 4.7 v v extvcc(hys) extv cc hysteresis 0.2 v oscillator f osc oscillator frequency (note 5), c osc = 43pf 265 300 335 khz f h /f osc maximum sync frequency ratio 1.3 f fcb(sync) fcb pin threshold for sync ramping negative 0.9 1.2 v pgood output v pgl pgood voltage low i pgood = 2ma 110 200 mv i pgood pgood leakage current v pgood = 5v 1 m a v pg pgood trip level v osense with respect to set output voltage v osense ramping negative C 6.0 C 7.5 C 9.5 % v osense ramping positive 6.0 7.5 9.5 % vid control vidv cc vid operating supply voltage 2.7 5.5 v i vidvcc vid supply current (note 6) vidv cc = 3.3v 0.01 5 m a r vfb/vosense resistance between v osense and v fb 10 k w r ratio resistor ratio accuracy programmed from 0.925v to 2.00v 0.05 % r pull-up vid0 to vid4 pull-up resistance (note 7) v diode = 0.6v 40 k w v idt vid input voltage threshold 0.4 1.0 1.6 v i vidleak vid input leakage current (note 7) vidv cc < vid < 7v 0.01 1 m a v pull-up vid pull-up voltage vidv cc = 3.3v 2.8 v vidv cc = 5v 4.5 v
4 ltc1736 typical perfor a ce characteristics uw efficiency vs load current (3 operating modes) load current (a) 0.001 efficiency (%) 60 70 80 burst sync cont 10 1736 g01 50 40 20 0.01 0.1 1 30 100 90 v in = 5v v out = 1.6v r s = 0.01 f o = 300khz extv cc open load current (a) 10ma 100ma 1a 10a efficiency (%) 1736 g02 100 90 80 70 60 50 40 v in = 5v extv cc = 5v v in = 24v v in = 15v input voltage (v) 0 70 efficiency (%) 75 80 85 90 100 5 10 15 20 1736 g03 25 30 95 extv cc = 5v v out = 1.6v figure 1 i out = 5a i out = 0.5a efficiency vs load current efficiency vs input voltage efficiency vs input voltage input voltage (v) 0 70 efficiency (%) 75 80 85 90 100 5 10 15 20 1736 g04 25 30 95 extv cc open v out = 1.6v figure 1 i out = 5a i out = 0.5a load current (a) 0 normalized v out (%) 0.2 0.1 8 1736 g05 0.3 0.4 2 4 6 12 10 0 fcb = 0v v in = 15v figure 1 load regulation load current (a) 0 0 i th voltage (v) 0.5 1.0 1.5 2.0 2.5 1 234 1736 g06 56 v in = 5v v out = 1.6v r sense = 0.01 f o = 300khz continuous mode burst mode operation synchronized f = f o i th voltage vs load current input and shutdown currents vs input voltage input voltage (v) 05 0 input current ( a) shutdown current ( a) 200 500 10 20 25 1736 g07 100 400 300 0 40 100 20 80 60 15 30 35 extv cc open shutdown extv cc = 5v all vid bits open intv cc line regulation input voltage (v) 0 intv cc voltage (v) 4 5 6 15 25 1736 g08 3 2 510 20 30 35 1 0 1ma load extv cc switch drop vs intv cc load current intv cc load current (ma) 0 extv cc ?intv cc (mv) 300 400 500 40 1736 g09 200 100 0 10 20 30 50
5 ltc1736 typical perfor a ce characteristics uw maximum current sense threshold vs normalized output voltage (foldback) normalized output voltage (%) 0 current sense threshold (mv) 40 50 60 100 1736 g10 30 20 0 25 50 75 10 80 70 v run/ss (v) 0 0 current sense threshold (mv) 20 40 60 80 1234 1736 g11 56 v sense(cm) = 1.6v common mode voltage (v) 0 current sense threshold (mv) 72 76 80 1736 g12 68 64 60 0.5 1 1.5 2 maximum current sense threshold vs v run/ss maximum current sense threshold vs sense common mode voltage maximum current sense threshold vs i th voltage v ith (v) 0 current sense threshold (mv) 30 50 70 90 2 1736 g13 10 ?0 20 40 60 80 0 ?0 ?0 0.5 1 1.5 2.5 v run/ss (v) 0 0 v ith (v) 0.5 1.0 1.5 2.0 2.5 1 234 1736 g15 56 v osense = 0.7v v ith vs v run/ss temperature ( c) 40 ?5 ? run/ss current ( a) ? 0 10 60 85 1736 g16 ? ? ? 35 110 135 v run/ss = 0v run/ss pin current vs temperature fcb pin current vs temperature temperature ( c) 40 ?5 ?.0 fcb current ( a) 0.6 0 10 60 85 1736 g17 0.8 0.2 0.4 35 110 135 v fcb = 0.85v maximum current sense threshold vs temperature temperature ( c) ?0 60 current sense threshold (mv) 65 70 75 80 ?5 10 35 60 1736 g18 85 110 135 v sense(cm) = 1.6v duty cycle (%) 0 0 average output current i out /i max (%) 20 40 60 80 100 20 40 60 80 1736 g14 100 f sync = f o i out /i max (synchronized) i out /i max (free run) output current vs duty cycle
6 ltc1736 typical perfor a ce characteristics uw oscillator frequency vs temperature temperature ( c) ?0 ?5 250 frequency (khz) 270 300 10 60 85 1736 g19 260 290 280 35 110 135 c osc = 47pf dynamic vid change, burst mode operation defeated v out 100mv/div i l 5a/div pgood 5v/div 1736 g20 dynamic vid change, burst mode operation enabled v out 100mv/div i l 5a/div pgood 5v/div 1736 g21 v out(ripple) (burst mode operation) v out 1v/div v run/ss 5v/div i l 5a/div 1736 g22 5ms/div v in = 15v v out = 1.6v r load = 0.16 w v out(ripple) (synchronized) v out 10mv/div i l 5a/div 1736 g23 10 m s/div ext sync (f = f o ) v in = 15v v out = 1.6v v out(ripple) (burst mode operation) v out 20mv/div 1736 g24 50 m s/div fcb = 5v v in = 15v v out = 1.6v i l 5a/div start-up load step (burst mode operation) load step (continuous mode) v out 20mv/div i l 5a/div 1736 g25 5 m s/div fcb = 5v v in = 15v v out = 1.6v v out 50mv/div i l 5a/div 1736 g26 10 m s/div 10ma to 11a load step fcb = 5v v in = 15v v out = 1.6v v out 50mv/div i l 5a/div 1736 g27 10 m s/div 0a to 11a load step fcb = 0v v in = 15v v out = 1.6v fcb = 0v fcb = pgood i load = 10ma i load = 50ma i load = 1.5a 20 m s/div 20 m s/div
7 ltc1736 pi fu ctio s uuu c osc (pin 1): external capacitor c osc from this pin to ground sets the operating frequency. run/ss (pin 2): combination of soft-start and run control inputs. a capacitor to ground at this pin sets the ramp time to full output current. the time is approximately 1.25s/ m f. forcing this pin below 1.5v causes the device to be shut down. in shutdown all functions are disabled. latchoff overcurrent protection is also invoked via this pin as described in the applications information section. i th (pin 3): error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0v to 2.4v. fcb (pin 4): forced continuous/synchronization input. tie this pin to ground for continuous synchronous opera- tion, to a resistive divider from the secondary output when using a secondary winding, or to intv cc to enable burst mode operation at low load currents. clocking this pin with a signal above 1.5v p-p disables burst mode operation but allows cycle skipping at low load currents and synchro- nizes the internal oscillator with the external clock. sgnd (pin 5): small-signal ground. all small-signal components such as c osc , c ss plus the loop compensa- tion resistors and capacitor(s) should single-point tie to this pin. this pin should, in turn, connect to pgnd. pgood (pin 6): open-drain logic output. pgood is pulled to ground when the voltage on the v osense pin is not within 7.5% of its set point. sense C (pin 7): the (C) input to the current comparator. sense + (pin 8): the (+) input to the current comparator. built-in offsets between sense C and sense + pins in conjunction with r sense set the current trip threshold. v fb (pin 9): divided down v osense voltage feeding the error amplifier of the regulator. the vid inputs program a resistive divider between v osense and sgnd; the tap point on the divider is v fb . the voltage on v fb is 0.8v when the output is in regulation. this pin can be bypassed to sgnd with 50pf to 100pf. v osense (pin 10): receives the remotely sensed feedback voltage from the output. vid0 to vid4 (pins 11 to 15): digital inputs for controlling the output voltage from 0.925v to 2.0v. table 1 specifies the v osense voltages for the 32 combinations of digital inputs. the lsb (vid0) represents 50mv increments in the upper voltage range (2.00v to 1.30v) and 25mv increments in the lower voltage range (1.275v to 0.925v). logic low = gnd, logic high = vidv cc or float. vidv cc (pin 16): vid input supply voltage. can range from 2.7v to 7v. typically this pin is tied to intv cc . extv cc (pin 17): input to the internal switch connected to intv cc . this switch closes and supplies v cc power whenever extv cc is higher than 4.7v. see extv cc con- nection in the applications information section. do not exceed 7v to this pin and ensure extv cc v in . pgnd (pin 18): driver power ground. this pin connects to the source of the bottom n-channel mosfet, the anode of the schottky diode and the (C) terminal of c in . bg (pin 19): high current gate drive for bottom n-channel mosfet. voltage swing at this pin is from ground to intv cc . intv cc (pin 20): output of the internal 5.2v regulator and extv cc switch. the driver and control circuits are pow- ered from this voltage. decouple to power ground with a 1 m f ceramic capacitor placed directly adjacent to the ic together with a minimum of 4.7 m f tantalum or other low esr capacitor. v in (pin 21): main supply pin. this pin must be closely decoupled to power ground. sw (pin 22): switch node connection to inductor and bootstrap capacitor. voltage swing at this pin is from a schottky diode (external) voltage drop below ground to v in . boost (pin 23): supply to topside floating driver. the bootstrap capacitor is returned to this pin. voltage swing at this pin is from a diode drop below intv cc to v in + intv cc . tg (pin 24): high current gate drive for top n-channel mosfet. this is the output of a floating driver with a voltage swing equal to intv cc superimposed on the switch node voltage sw.
8 ltc1736 fu ctio al diagra uu w operatio u (refer to functional diagram) main control loop the ltc1736 uses a constant frequency, current mode step-down architecture. during normal operation, the top mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the main current comparator i1 resets the rs latch. the peak inductor current at which i1 resets the rs latch is controlled by the voltage on pin i th , which is the output of the error amplifier ea. pin v osense , described in the pin functions, allows ea to receive an output feedback voltage v fb from the internal resistive divider. when the load current increases, it causes a slight decrease in v fb relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current com- parator i2, or the beginning of the next cycle. the top mosfet driver is powered from a floating bootstrap capacitor c b . this capacitor is normally re- charged from intv cc through an external schottky diode when the top mosfet is turned off. as v in decreases towards v out , the converter will attempt to turn on the top mosfet continuously (dropout). a dropout counter detects this condition and forces the top mosfet to turn off for about 500ns every tenth cycle to recharge the bootstrap capacitor. sw + + 0.86v 0.74v + 0.55v 2.4v 0.8v 47pf 0.86v i1 + i2 + ea a burst disable fc ov b + 4.8v irev + + f fc s r q drop out det 0.8v ref switch logic sd 6v run/ss c ss r c v fb 40k 1.2 a run soft start + over- current latch-off sd i th c c 0.17 a osc 4(v fb ) buffered i th slope comp + + 3mv icmp r2 10k r1 sgnd v fb v osense 2k 45k bot top on force bot 45k 30k 30k sense + sense sync 1.2v 0.8v c top uvl bot intv cc 5.2v ldo reg v in + c intvcc v out v sec intv cc bg pgnd v in v in boost tg intv cc c b d b d 1 c osc + c in + c sec + c out extv cc fcb r4 r3 c osc r sense 1736 fd 1 pgood 6 9 10 5 vidv cc vid4 intv cc 15 vid3 14 vid2 13 vid1 12 vid0 11 4 21 23 24 22 20 19 18 17 7 8 3 2 + vid decoder 16 g m =1.3m
9 ltc1736 operatio u (refer to functional diagram) the main control loop is shut down by pulling pin 2 (run/ ss) low. releasing run/ss allows an internal 1.2 m a current source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, i th is gradually re- leased allowing normal operation to resume. if v out has not reached 70% of its final value when c ss has charged to 4.1v, latchoff can be invoked as described in the applications information section. the internal oscillator can be synchronized to an external clock applied to the fcb pin and can lock to a frequency between 90% and 130% of its nominal rate set by capaci- tor c osc . an overvoltage comparator ov guards against transient overshoots (> 7.5%) as well as other more serious condi- tions that may overvoltage the output. in this case, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. foldback current limiting for an output shorted to ground is provided by amplifier a. as v fb drops below 0.6v, the buffered i th input to the current comparator is gradually pulled down to a 0.86v clamp. this reduces peak inductor current to about 1/4 of its maximum value. low current operation the ltc1736 has three low current modes controlled by the fcb pin. burst mode operation is selected when the fcb pin is above 0.8v (typically tied to intv cc ). during burst mode operation, if the error amplifier drives the i th voltage below 0.86v, the buffered i th input to the current comparator will be clamped at 0.86v. the inductor current peak is then held at approximately 20mv/r sense (about 1/ 4 of maximum output current). if i th then drops below 0.5v, the burst mode comparator b will turn off both mosfets to maximize efficiency. the load current will be supplied solely by the output capacitor until i th rises above the 60mv hysteresis of the comparator and switch- ing is resumed. burst mode operation is disabled by comparator f when the fcb pin is brought below 0.8v. this forces continuous operation and can assist second- ary winding regulation. when the fcb pin is driven by an external oscillator, a low noise cycle-skipping mode is invoked and the internal oscillator is synchronized to the external clock by com- parator c. in this mode the 25% minimum inductor current clamp is removed, providing constant frequency discontinuous operation over the widest possible output current range. this constant frequency operation is not quite as efficient as burst mode operation, but provides a lower noise, constant frequency spectrum. the fcb pin is tied to ground when forced continuous operation is desired. this operation is the least efficient mode, but is desirable in certain applications. the output can source or sink current in this mode. when sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levels beware. foldback current, short-circuit detection and short-circuit latchoff the run/ss capacitor, c ss , is used initially to limit the inrush current of the switching regulator. after the con- troller has been started and been given adequate time to charge up the output capacitors and provide full load current, c ss is used as a short-circuit time-out circuit. if the output voltage falls to less than 70% of its nominal output voltage, c ss begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. if the condition lasts for a long enough period as determined by the size of the c ss , the controller will be shut down until the run/ss pin voltage is recycled. this built-in latchoff can be overridden by providing a current >5 m a at a compliance of 5v to the run/ss pin. this current shortens the soft-start period but also prevents net discharge of c ss during an overcurrent and/or short- circuit condition. foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled.
10 ltc1736 operatio u (refer to functional diagram) intv cc /extv cc power power for the top and bottom mosfet drivers and most of the internal circuitry of the ltc1736 is derived from the intv cc pin. when the extv cc pin is left open, an internal 5.2v low dropout regulator supplies the intv cc power from v in . if extv cc is raised above 4.7v, the internal regulator is turned off and an internal switch connects extv cc to intv cc . this allows a high efficiency source, such as the notebook main 5v system supply or a second- ary output of the converter itself, to provide the intv cc power. voltages up to 7v can be applied to extv cc for additional gate drive capability. to provide clean start-up and to protect the mosfets, undervoltage lockout is used to keep both mosfets off until the input voltage is above 3.5v. vid control bits vid0 to vid4 are logic inputs setting the output volt- age using an internal 5-bit dac as a feedback resistive voltage divider. the output voltage can be set in 50mv or 25mv increments from 0.925v to 2.0v according to table 1. pins vid0 to vid4 are internally pulled up to vidv cc . pgood a window comparator monitors the output voltage and its open-drain output is pulled low when the divided down output voltage is not within 7.5% of the reference voltage of 0.8v. r mv i sense max = 50 c osc selection for operating frequency and synchronization the choice of operating frequency and inductor value is a trade-off between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses, both gate charge loss and transition loss. however, lower frequency operation re- quires more inductance for a given amount of ripple current. the ltc1736 uses a constant-frequency architecture with the frequency determined by an external oscillator capaci- tor c osc . each time the topside mosfet turns on, the voltage on c osc is reset to ground. during the on-time c osc is charged by a fixed current. when the voltage on the capacitor reaches 1.19v, c osc is reset to ground. the process then repeats. the value of c osc is calculated from the desired operating frequency assuming no external clock input on the fcb pin: applicatio s i for atio wu u u the basic ltc1736 application circuit is shown in figure 1 on the first page of this data sheet. external component selection is driven by the load requirement and begins with the selection of r sense . once r sense is known, c osc and l can be chosen. next, the power mos- fets and d1 are selected. the operating frequency and the inductor are chosen based largely on the desired amount of ripple current. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient specifications. the circuit shown in figure 1 can be configured for operation up to an input voltage of 28v (limited by the external mosfets). r sense selection for output current r sense is chosen based on the required output current. the ltc1736 current comparator has a maximum thresh- old of 75mv/r sense and an input common mode range of sgnd to 1.1(intv cc ). the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, d i l . allowing a margin for variations in the ltc1736 and external component values yields:
11 ltc1736 applicatio s i for atio wu u u cpf frequency osc () .( ) = ? ? 16110 11 7 a graph for selecting c osc versus frequency is given in figure 2. the maximum recommended switching fre- quency is 550khz . the internal oscillator runs at its nominal frequency (f o ) when the fcb pin is pulled high to intv cc or connected to ground. clocking the fcb pin above and below 0.8v will cause the internal oscillator to lock to an external clock signal with a frequency between 0.9f o and 1.3f o . the clock high level must exceed 1.3v for at least 0.3 m s, and the clock low level must be less than 0.3v for at least 0.3 m s. the top mosfet turn-on will synchronize with the rising edge of the external clock. attempting to synchronize to too high an external fre- quency (above 1.3f o ) can result in inadequate slope com- pensation and possible loop instability at high duty cycles. if this condition exists simply lower the value of c osc so f ext = f o according to figure 2. cycles to recharge the bootstrap capacitor. this minimizes audible noise while maintaining reasonably high efficiency. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate-charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current d i l decreases with higher induc- tance or frequency and increases with higher v in or v out : d i fl v v v l out out in = ? ? 1 1 ()( ) accepting larger values of d i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is d i l = 0.3 to 0.4(i max ). remember, the maximum d i l occurs at the maximum input voltage. the inductor value also has an effect on low current operation. the transition to low current operation begins when the inductor current reaches zero while the bottom mosfet is on. burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher d i l ) will cause this to occur at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, operating frequency (khz) 0 100 200 300 400 500 600 c osc value (pf) 1736 f02 100.0 87.5 75.0 62.5 50.0 37.5 25.0 12.5 0 when synchronized to an external clock, burst mode op- eration is disabled but the inductor current is not allowed to reverse. the 25% minimum inductor current clamp present in burst mode operation is removed, providing constant frequency discontinuous operation over the wid- est possible output current range. in this mode the synchronous mosfet is forced on once every 10 clock figure 2. timing capacitor value
12 ltc1736 applicatio s i for atio wu u u molypermalloy or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductance selected. as induc- tance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m m . toroids are very space efficient, especially when you can use several layers of wire. be- cause they generally lack a bobbin, mounting is more difficult. however, designs for surface mount are available that do not increase the height significantly. power mosfet and d1 selection two external power mosfets must be selected for use with the ltc1736: an n-channel mosfet for the top (main) switch and an n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak gate drive levels are set by the intv cc voltage. this voltage is typically 5.2v during start-up. (see extv cc pin connection.) consequently, logic-level thresh- old mosfets must be used in most ltc1736 applica- tions. the only exception is when low input voltage is expected (v in < 5v); then, sublogic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss specification for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , reverse transfer capacitance c rss , input voltage and maximum output current. when the ltc1736 is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous switch duty cycle vv v out in in out in = = the mosfet power dissipations at maximum output current are given by: p v v ir kv i c f p vv v ir main out in max ds on in max rss sync in out in max ds on = () + () + ()( )( )() = () + () 2 2 2 1 1 d d () () where d is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for tran- sition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch is nearly 100%. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet characteristics. the constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. the schottky diode d1 shown in figure 1 conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. a 3a schottky is generally a good size for 10a to 12a regulators due to the relatively small average current. kool m m is a registered trademark of magnetics, inc.
13 ltc1736 applicatio s i for atio wu u u c out required esr < 2.2 r sense c out > 1/(8fr sense ) the first condition relates to the ripple current into the esr of the output capacitance while the second term guaran- tees that the output capacitance does not significantly discharge during the operating frequency period due to ripple current. the choice of using smaller output capaci- tance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage at or below 50mv. the i th pin opti-loop compensation compo- nents can be optimized to provide stable, high perfor- mance transient response regardless of the output capaci- tors selected. the selection of output capacitors for cpu or other appli- cations with large load current transients is primarily determined by the voltage tolerance specifications of the load. the resistive component of the capacitor, esr, multiplied by the load current change plus any output voltage ripple must be within the voltage tolerance of the load (cpu). the required esr due to a load current step is: r esr < d v/ d i where d i is the change in current from full load to zero load (or minimum load) and d v is the allowed voltage deviation (not including any droop due to finite capacitance). the amount of capacitance needed is determined by the maximum energy stored in the inductor. the capacitance must be sufficient to absorb the change in inductor current when a high current to low current transition occurs. the opposite load current transition is generally determined by the control loop opti-loop components, so make sure not to over compensate and slow down the response. the minimum capacitance to assure the inductors energy is adequately absorbed is: c li vv out out > () () d d 2 2 where d i is the change in load current. larger diodes can result in additional transition losses due to their larger junction capacitance. the diode may be omitted if the efficiency loss can be tolerated. c in selection in continuous mode, the source current of the top n-channel mosfet is a square wave of duty cycle v out / v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ii v v v v rms o max out in in out @ ? ? ? ? () / 1 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. c out selection the selection of c out is primarily determined by the effective series resistance (esr) to minimize voltage ripple. the output ripple ( d v out ) in continuous mode is deter- mined by: dd v i esr fc out l out ?+ ? ? ? ? 1 8 where f = operating frequency, c out = output capaci- tance, and d i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. typically, once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. with d i l = 0.3i out(max) the output ripple will be less than 50mv at max v in assuming:
14 ltc1736 applicatio s i for atio wu u u manufacturers such as nichicon, united chemicon and sanyo can be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest (esr)(size) product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recommended to reduce the inductance effects. in surface mount applications multiple capacitors may need to be used in parallel to meet the esr, rms current handling, and load step requirements of the application. aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. spe- cial polymer surface mount capacitors offer very low esr but have much lower capacitive density per unit volume than other capacitor types. these capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. tantalum capacitors offer the highest capaci- tance density and are often used as output capacitors for switching regulators having controlled soft-start. several excellent surge-tested choices are the avx tps, avx tpsv or the kemet t510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors can be used in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long-term reliability. a typical application will require several to many aluminum electrolytic capacitors in parallel. a combina- tion of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. other capacitor types include nichicon pl series, nec neocap, panasonic sp and sprague 595d series. consult manufacturers for other specific recommendations. like all components, capacitors are not ideal. each ca- pacitor has its own benefits and limitations. combina- tions of different capacitor types have proven to be a very cost effective solution. remember also to include high frequency decoupling capacitors. they should be placed as close as possible to the power pins of the load. any inductance present in the circuit board traces negates their usefulness. intv cc regulator an internal p-channel low dropout regulator produces the 5.2v supply that powers the drivers and internal circuitry within the ltc1736. the intv cc pin can supply a maxi- mum rms current of 50ma and must be bypassed to ground with a minimum of 4.7 m f tantalum, 10 m f special polymer or low esr type electrolytic capacitor. good bypassing is required to supply the high transient currents required by the mosfet gate drivers. higher input voltage applications in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the ltc1736 to be exceeded. the system supply current is normally dominated by the gate charge current. additional loading of intv cc also needs to be taken into account for the power dissipation calculations. the total intv cc current can be supplied by either the 5.2v internal linear regulator or by the extv cc input pin. when the voltage applied to the extv cc pin is less than 4.7v, all of the intv cc current is supplied by the internal 5.2v linear regulator. power dissipation for the ic in this case is highest: (v in )(i intvcc ), and overall efficiency is lowered. the gate charge is dependent on operating frequency as discussed in the efficiency considerations section. the junction tempera- ture can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the ltc1736g is limited to less than 17ma from a 30v supply when not using the extv cc pin as follows: t j = 70 c + (17ma)(30v)(110 c/w) = 126 c use of the extv cc input pin reduces the junction tempera- ture to: t j = 70 c + (17ma)(5v)(110 c/w) = 79 c to prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum v in . extv cc connection the ltc1736 contains an internal p-channel mosfet switch connected between the extv cc and intv cc pins. whenever the extv cc pin is above 4.7v the internal 5.2v
15 ltc1736 applicatio s i for atio wu u u regulator shuts off, the switch closes and intv cc power is supplied via extv cc until extv cc drops below 4.5v. this allows the mosfet gate drive and control power to be derived from the output or other external source during normal operation. when the output is out of regulation (start-up, short circuit) power is supplied from the internal regulator. do not apply greater than 7v to the extv cc pin and ensure that extv cc < v in . significant efficiency gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(efficiency). for 5v regulators this simply means connecting the extv cc pin directly to v out . however, for vid programmed regulators and other lower voltage regulators, additional circuitry is required to de- rive intv cc power from the output. the following list summarizes the three possible connec- tions for extv cc: 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5.2v regulator resulting in a low current efficiency penalty of up to 10% at high input voltages. 2. extv cc connected to an external supply (this option is the most likely used). if an external supply is available in the 5v to 7v range, such as notebook main 5v system power, it may be used to power extv cc provid- ing it is compatible with the mosfet gate drive requirements. this is the typical case as the 5v power is almost always present and is derived by another high efficiency regulator. 3. extv cc connected to an output-derived boost net- work. for this low output voltage regulator, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. this can be done with either the inductive boost winding or the capacitive charge pump circuits. refer to the ltc1735 data sheet for details. the charge pump has the advantage of simple magnetics. output voltage programming the output voltage is digitally set to levels between 0.925v and 2.00v using the voltage identification (vid) inputs vid0 to vid4. the internal 5-bit dac configured as a precision resistive voltage divider sets the output voltage in 50mv or 25mv increments according to table 1. the vid codes (00000-11110) are engineered to be com- patible with intel mobile pentium ii and pentium iii pro- cessor specifications for output voltages from 0.925v to 2.00v. the lsb (vid0) represents 50mv increments in the upper voltage range (1.30v to 2.00v) and 25mv increments in the lower voltage range (0.925v to 1.275v). the msb is vid4. when all bits are low, or grounded, the output voltage is 2.00v. between the v fb pin and ground is a variable resistor, r1, whose value is controlled by the five input pins (vid0 to vid4). another resistor, r2, between the v osense and the v fb pins completes the resistive divider. the output volt- age is thus set by the ratio of (r1 + r2) to r1. the ltc1736 has remote sense capability. the top of the internal resistive divider is connected to v osense , and it is referenced to the sgnd pin. this allows a kelvin connec- tion for remotely sensing the output voltage directly across the load, eliminating any pc board trace resistance errors. each vid digital input is pulled up by a 40k resistor in series with a diode from vidv cc . therefore, it must be grounded to get a digital low input, and can be either floated or connected to vidv cc to get a digital high input. the series diode is used to prevent the digital inputs from being damaged or clamped if they are driven higher than vidv cc . the digital inputs accept cmos voltage levels. vidv cc is the supply voltage for the vid section. it is normally connected to intv cc but can be driven from other sources such as a 3.3v supply. if it is driven from another source, that source must be in the range of 2.7v to 5.5v and must be alive prior to enabling the ltc1736.
16 ltc1736 applicatio s i for atio wu u u table 1. vid output voltage programming vid4 vid3 vid2 vid1 vid0 v out (v) 00000 2.000v 00001 1.950v 00010 1.900v 00011 1.850v 00100 1.800v 00101 1.750v 00110 1.700v 00111 1.650v 01000 1.600v 01001 1.550v 01010 1.500v 01011 1.450v 01100 1.400v 01101 1.350v 01110 1.300v 01111 * 10000 1.275v 10001 1.250v 10010 1.225v 10011 1.200v 10100 1.175v 10101 1.150v 10110 1.125v 10111 1.100v 11000 1.075v 11001 1.050v 11010 1.025v 11011 1.000v 11100 0.975v 11101 0.950v 11110 0.925v 11111 ** note: *, ** represents codes without a defined output voltage as specified in intel specifications. the ltc1736 interprets these codes as valid inputs and produces output voltages as follows: [01111] = 1.250v, [11111] = 0.900v. topside mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. note that the voltage across c b is about a diode drop below intv cc . when the topside mosfet is to be turned on, the driver places the c b voltage across the gate-source of the mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage sw rises to v in and the boost pin rises to v in + intv cc . the value of the boost capacitor c b needs to be 100 times greater than the total input capacitance of the topside mosfet. in most applications 0.1 m f to 0.33 m f is adequate. the reverse breakdown on d b must be greater than v in(max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if you make a change and the input current decreases, then you improve the efficiency. if there is no change in input current, then there is no change in efficiency. sense + /sense C pins the common mode input range of the current comparator is from 0v to 1.1(intv cc ). continuous linear operation is guaranteed throughout this range allowing output volt- ages anywhere from 0.8v to 7v (although the vid control pins only program a 0.925v to 2.00v output range). a differential npn input stage is used and is biased with internal resistors from an internal 2.4v source as shown in the functional diagram. this causes current to flow out of both sense pins to the main output. this forces a minimum load current which is sunk by the internal resistive divider resistors r1 and r2. the maximum current flowing out of the sense pins is: i sense + + i sense C = (2.4v C v out )/24k remember to take this current into account if resistance is placed in series with the sense pins for filtering.
17 ltc1736 applicatio s i for atio wu u u soft-start/run function the run/ss pin is a multipurpose pin that provides a soft- start function and a means to shut down the ltc1736. soft-start reduces surge currents from v in by gradually increasing the controllers current limit i th(max) . this pin can also be used for power supply sequencing. pulling the run/ss pin below 1.5v puts the ltc1736 into a low quiescent current shutdown (i q < 25 m a). this pin can be driven directly from logic as shown in figure 3. releas- ing the run/ss pin allows an internal 1.2 m a current source to charge up the external soft-start capacitor c ss. if run/ss has been pulled all the way to ground there is a delay before starting of approximately: t v a csfc delay ss ss = m =m () 15 12 125 . . ./ when the voltage on run/ss reaches 1.5v the ltc1736 begins operating with a current limit at approximately 25mv/r sense . as the voltage on run/ss increases from 1.5v to 3.0v, the internal current limit is increased from 25mv/r sense to 75mv/r sense . the output current limit ramps up slowly, taking an additional 1.25s/ m f to reach full current. the output current thus ramps up slowly reducing the starting surge current required from the input power supply. diode d1 in figure 3 reduces the start delay while allowing c ss to charge up slowly for the soft-start function. this diode and c ss can be deleted if soft-start is not needed. the run/ss pin has an internal 6v zener clamp (see functional diagram). fault conditions: overcurrent latchoff the run/ss pin also provides the ability to shut off the controller and latchoff when an overcurrent condition is detected. the run/ss capacitor c ss is used initially to turn on and limit the inrush current of the controller. after the controller has been started and given adequate time to charge up the output capacitor and provide full load current, c ss is used as a short-circuit timer. if the output voltage falls to less than 70% of its nominal output voltage after c ss reaches 4.1v , the assumption is made that the output is in a severe overcurrent and/or short-circuit condition and c ss begins discharging. if the condition lasts for a long enough period as determined by the size of c ss , the controller will be shut down until the run/ss pin voltage is recycled. this built-in latchoff can be overridden by providing a current > 5 m a at a compliance of 5v to the run/ss pin as shown in figure 4. this current shortens the soft-start period but also prevents net discharge of the run/ss capacitor during a severe overcurrent and/or short-circuit condition. when deriving the 5 m a current from v in as in figure 4a, current latchoff is always defeated. a diode connecting this pull-up resistor to intv cc , as in figure 4b, eliminates any extra supply current during controller shut- down while eliminating the intv cc loading from prevent- ing controller start-up. if the voltage on c ss does not exceed 4.1v, the overcurrent latch is not armed and the function is disabled. figure 3. run/ss pin interfacing 3.3v or 5v run/ss d1 run/ss (a) (b) c ss c ss 1736 f03 3.3v or 5v run/ss v in intv cc run/ss d1 (a) (b) d1 c ss r ss c ss r ss 1736 f04 figure 4. run/ss pin interfacing with latchoff defeated
18 ltc1736 applicatio s i for atio wu u u why should you defeat overcurrent latchoff? during the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. defeating this feature will easily allow trouble- shooting of the circuit and pc layout. the internal short- circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. after the design is complete, a decision can be made whether to enable the latchoff feature. the value of the soft-start capacitor c ss will need to be scaled with output voltage, output capacitance and load current characteristics. the minimum soft-start capaci- tance is given by: c ss > (c out )(v out )(10 C4 )(r sense ) the minimum recommended soft-start capacitor of c ss = 0.1 m f will be sufficient for most applications. fault conditions: current limit and current foldback the ltc1736 current comparator has a maximum sense voltage of 75mv resulting in a maximum mosfet current of 75mv/r sense . the ltc1736 includes current foldback to help further limit load current when the output is shorted to ground. the foldback circuit is active even when the overload shutdown latch described above is defeated. if the output falls by more than half, then the maximum sense voltage is progressively lowered from 75mv to 30mv. under short-circuit conditions with very low duty cycle, the ltc1736 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be conducting the peak current. the short-circuit ripple current is determined by the minimum on-time t on(min) of the ltc1736 (less than 200ns), the input voltage, and inductor value: d i l(sc) = t on(min) v in /l. the resulting short circuit current is: i mv r i sc sense lsc =+ 30 1 2 d () the current foldback function is always active and is not effected by the current latchoff function. fault conditions: output overvoltage protection (crowbar) the output overvoltage crowbar is designed to blow a system fuse in the input lead when the output of the regulator rises much higher than nominal levels. this condition causes huge currents to flow, much greater than in normal operation. this feature is designed to protect against a shorted top mosfet; it does not protect against a failure of the controller itself. the comparator (ov in the functional diagram) detects overvoltage faults greater than 7.5% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is forced on. the bottom mosfet remains on continuously for as long as the ov condition persists; if v out returns to a safe level, normal operation automatically resumes. note that vid controlled output voltage decreases may cause the overvoltage protection to be momentarily activated. this will not cause permanent latchoff nor will it disrupt the desired voltage change. with soft-latch overvoltage protection, dynamic vid code changes are allowed and the overvoltage protection tracks the new vid code, always protecting the load (cpu). if dynamic vid code changes are anticipated and the mini- mum load current is light, it may be necessary to either force continuous operation by pulling fcb low during the transition to maximize current sinking capability or con- nect pgood to fcb to automatically force continuous operation during vid transitions.
19 ltc1736 minimum on-time considerations minimum on-time t on(min) is the smallest amount of time that the ltc1736 is capable of turning the top mosfet on and off again. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on- time limit and care should be taken to ensure that: t v vf on min out in () () < if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc1736 will begin to skip cycles. the output voltage will continue to be regulated, but the ripple current and voltage will increase. the minimum on-time for the ltc1736 in a properly configured application is generally less than 200ns. how- ever, as the peak sense voltage decreases, the minimum on-time gradually increases as shown in figure 5. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with corre- spondingly larger current and voltage ripple. if an application can operate close to the minimum on- time limit, an inductor must be chosen that is low enough in value to provide sufficient ripple amplitude to meet the minimum on-time requirement. as a general rule keep the applicatio s i for atio wu u u inductor ripple current equal or greater than 30% of i out(max) at v in(max) . fcb pin operation when the dc voltage on the fcb pin drops below its 0.8v threshold, continuous mode operation is forced. in this case, the top and bottom mosfets continue to be driven synchronously regardless of the load on the main output. burst mode operation is disabled and current reversal is allowed in the inductor. in addition to providing a logic input to force continuous synchronous operation and external synchronization, the fcb pin provides a means to regulate a flyback winding output. during continuous mode, current flows continu- ously in the transformer primary. the secondary winding(s) draw current only when the bottom synchronous switch is on. when primary load currents are low and/or the v in /v out ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. forced con- tinuous operation will support secondary windings pro- vided there is sufficient synchronous switch duty factor. thus, the fcb input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. with the loop in continuous mode, the auxiliary output may nominally be loaded without regard to the primary output load. the secondary output voltage v sec is normally set as shown in the functional diagram by the turns ratio n of the transformer: v sec @ (n + 1) v out however, if the controller goes into burst mode operation and halts switching due to a light primary load current, then v sec will droop. an external resistive divider from v sec to the fcb pin sets a minimum voltage v sec(min) : vv r r sec min () . ?+ ? ? ? ? 08 1 4 3 if v sec drops below this level, the fcb voltage forces continuous switching operation until v sec is again above its minimum. ? i l /i out(max) (%) 0 minimum on-time (ns) 100 150 40 1736 f05 50 0 10 20 30 250 200 figure 5. minimum on-time vs d i l
20 ltc1736 in order to prevent erratic operation if no external connec- tions are made to the fcb pin, the fcb pin has a 0.17 m a internal current source pulling the pin high. remember to include this current when choosing resistor values r3 and r4. the internal ltc1736 oscillator can be synchronized to an external oscillator by clocking the fcb pin with a signal above 1.5v p-p . when synchronized to an external fre- quency, burst mode operation is disabled, but cycle skip- ping is allowed at low load currents since current reversal is inhibited. the bottom gate will come on every 10 clock cycles to assure the boostrap cap, c b , is kept refreshed. the rising edge of an external clock applied to the fcb pin starts a new cycle. the range of synchronization is from 0.9f o to 1.3f o , with f o set by c osc . attempting to synchronize to a higher frequency than 1.3f o can result in inadequate slope comensation and cause loop instability with high duty cycles. if loop instability is observed while synchronized, additional slope compensation can be obtained by simply decreasing c osc . the following table summarizes the possible states avail- able on the fcb pin: table 2 fcb pin condition dc voltage: 0v to 0.7v burst disabled/forced continuous current reversal enabled dc voltage: > 0.9v burst mode operation, no current reversal feedback resistors regulating a secondary winding ext clock: (0v to v fcbsync ) burst mode operation disabled (v fcbsync 3 1.5v) no current reversal efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% - (l1 + l2 + l3 + ...) applicatio s i for atio wu u u where l1, l2, etc., are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1736 circuits: 1) ltc1736 v in current, 2) intv cc current, 3) i 2 r losses, 4) topside mosfet transi- tion losses. 1. the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (< 0.1%) loss that increases with v in . 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom-side mosfets. supplying intv cc power through the extv cc switch input from an output-derived or other high efficiency source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(effi- ciency). for example, in a 15v to 1.8v application, 10ma of intv cc current results in approximately 1.2ma of v in current. this reduces the low current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the mosfets, inductor and current shunt. in continuous mode the average output current flows through l and r sense , but is chopped between the topside main mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 0.02 w , r l = 0.03 w , and r sense = 0.01 w , then the total resistance is
21 ltc1736 applicatio s i for atio wu u u 0.06 w . this results in losses ranging from 3% to 17% as the output current increases from 1a to 5a for a 1.8v output, or 4% to 20% for a 1.5v output. efficiency varies as the inverse square of v out for the same external components and power level. i 2 r losses cause the efficiency to drop at high output currents. 4. transition losses apply only to the topside mosfet(s), and only become significant when operating at high input voltages (typically 12v or greater). transition losses can be estimated from: transition loss = (1.7)(v in 2 )(i o(max) )(c rss )(f) other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resis- tance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switch- ing frequency. a 25w supply will typically require a minimum of 20 m f to 40 m f of capacitance having a maxi- mum of 0.01 w to 0.02 w of esr. other losses including schottky conduction losses during dead-time and induc- tor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load (esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti- loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a pre- dominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full-load current having a rise time of 1 m s to 10 m s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second-order overshoot/dc ratio cannot be used determine phase margin. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. improve transient response and reduce output capacitance with active voltage positioning fast load transient response, limited board space and low cost are requirements of microprocessor power supplies. active voltage positioning improves transient response and reduces the output capacitance required to power a microprocessor where a typical load step can be from 0.2a
22 ltc1736 to 15a in 100ns or 15a to 0.2a in 100ns. the voltage at the microprocessor must be held to about 0.1v of nominal in spite of these load current steps. since the control loop cannot respond this fast, the output capacitors must supply the load current until the control loop can respond. capacitor esr and esl primarily determine the amount of droop or overshoot in the output voltage. normally, sev- eral capacitors in parallel are required to meet micropro- cessor transient requirements. active voltage positioning is a form of deregulation. it sets the output voltage high for light loads and low for heavy loads. when load current suddenly increases, the output voltage starts from a level higher than nominal so the output voltage can droop more and stay within the specified voltage range. when load current suddenly decreases the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range. less output capacitance is required when voltage positioning is used because more voltage variation is allowed on the output capacitors. active voltage positioning can be implemented using the opti-loop architecture of the ltc1736 with two external resistors. an input voltage offset is introduced when the error amplifier has to drive a resistive load. this offset is limited to 30mv at the input of the error amplifier. the resulting change in output voltage is the product of input offset and the feedback voltage divider ratio. figure 6 shows a cpu-core-voltage regulator with active voltage positioning. resistors r1 and r5 force the input voltage offset that sets the output voltage according to the load current level. to select values for r1 and r5, first determine the amount of output deregulation allowed. the actual specification for a typical microprocessor allows the output to vary 0.112v. the ltc1736 output voltage 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 c osc run/ss i th fcb sgnd pgood sense sense + v fb v osense vid0 vid1 tg boost sw v in intv cc bg pgnd extv cc vidv cc vid4 vid3 vid2 ltc1736 c5 1000pf c6 47pf vid0 vid1 vid2 vid3 vid4 vid input c7 330pf c3 100pf c1 39pf c4 100pf c2 0.1 f power good r2 100k r5 100k r4 100k r3 680k r1 27k + c10 1 f 5v (optional) c18 1 f c12 to c14 10 f 35v c11 4.7 f 10v d1 cmdsh-3 c8 0.1 f d2 mbrs340 c9 0.22 f m1 fds6680a l1 1 h r6 0.003 m2, m3 fds6680a 2 1736 f06 c15 to c17 180 f/4v 4 v out 0.9v to 2v 15a gnd gnd v in 7.5v to 24v + c10, c18: taiyo yuden jmk107bj105 c11: kemet t494a475m010as c12 to c14: taiyo yuden gmk325f106 c15 to c17: panasonic eefue0g181r d1: central semi cmdsh-3 d2: motorola mbrs340 l1: panasonic etqp6f1r0sa m1 to m3: fairchild fds6680a r6: irc lrf2512-01-r003-j u1: linear technology LTC1736Cg figure 6. cpu-core-voltage regulator with active voltage positioning applicatio s i for atio wu u u
23 ltc1736 accuracy is 1%, so the output transient voltage cannot exceed 0.097v. at v out = 1.5v, the maximum output voltage change controlled by the i th pin would be: d= = = v input offset v v v v mv osense out ref .. . 003 15 08 56 with optimum resistor values at the i th pin, the output voltage will swing from 1.55v at minimum load to 1.44v at full load. at this output voltage, active voltage position- ing provides an additional 56mv to the allowable transient voltage on the output capacitors, a 58% improvement over the 97mv allowed without active voltage positioning. the next step is to calculate the i th pin voltage, v ith , scale factor. the v ith scale factor reflects the i th pin voltage required for a given load current. v ith controls the peak sense resistor voltage, which represents the dc output current plus one half of the peak-to-peak inductor current. the no load to full load v ith range is from 0.3v to 2.4v, which controls the sense resistor voltage from 0v to the d v sense(max) voltage of 75mv. the calculated v ith scale factor with a 0.003 w sense resistor is: v scale factor v range sense sistor value v vv v va ith ith sense max = d == re (. . ) . . ./ () 24 03 0003 0 075 0 084 v ith at any load current is: vi i v scale factor v offset ith out dc l ith ith =+ d ? ? ? ? ? ? + () 2 at full load current: va a va v v ith max pp () . / . . =+ ? ? ? ? ? ? + = - 15 5 2 0 084 0 3 177 at minimum load current: va a va v v ith min pp () ../. . =+ ? ? ? ? ? ? + = - 02 2 2 0 084 0 3 040 in this circuit, v ith changes from 0.40v at light load to 1.77v at full load, a 1.37v change. notice that d i l , the peak-to-peak inductor current, changes from light load to full load. increasing the dc inductor current decreases the permeability of the inductor core material, which de- creases the inductance and increases d i l . the amount of inductance change is a function of the inductor design. to create the 30mv input offset, the gain of the error amplifier must be limited. the desired gain is: a v input offset v v v ith = d == 137 2003 22 8 . (. ) . connecting a resistor to the output of the transconductance error amplifier will limit the voltage gain. the value of this resistor is: r a error amplifier g ms k ith v m === 22 8 13 17 54 . . . to center the output voltage variation, v ith must be centered so that no i th pin current flows when the output voltage is nominal. v ith(nom) is the average voltage be- tween v ith at maximum output current and minimum output current: v vv v vv vv ith nom ith max ith min ith min () () () () .. .. =+ =+= 2 177 040 2 0 40 1 085 the thevenin equivalent of the gain limiting resistance value of 17.54k is made up of a resistor r5 that sources current into the i th pin and resistor r1 that sinks current to sgnd. applicatio s i for atio wu u u
24 ltc1736 v in = 12v v out = 1.5v 1.5v 100mv/div 15a 0a 10a/div output voltage load current 50 m s/div 1736 f07 figure 7. normal transient response (without r1, r5) v in = 12v v out = 1.5v 1.582v 1.5v 1.418v 100mv/div 15a 0a 10a/div 50 m s/div 1736 f08 figure 8. transient response with active voltage positioning output voltage load current to calculate the resistor values, first determine the ratio between them: k vv v vv v intvcc ith nom ith nom === .. . . () () 52 1085 1 085 379 v intvcc is equal to v extvcc or 5.2v if extvcc is not used. resistor r5 is: rk r k k ith 4 1 3 79 1 17 54 84 0 =+ = + = () (. ). . resistor r1 is: r kr k k k ith 1 1 3 79 1 17 54 379 22 17 = + = + = () (. ). . . unfortunately, pcb noise can add to the voltage developed across the sense resistor, r6, causing the ith pin voltage to be slightly higher than calculated for a given output current. the amount of noise is proportional to the output current level. this pcb noise does not present a serious problem but it does change the effective value of r6 so the calculated values of r1 and r5 may need to be adjusted to achieve the required results. since pcb noise is a function of the layout, it will be the same on all boards with the same layout. figures 7 and 8 show the transient response before and after active voltage positioning is implemented. notice that the output voltage droop and overshoot levels dont change but the peak-to-peak output voltage reduces con- siderably with active voltage positioning. refer to design solutions 10 for more information about active voltage positioning. automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. but before you connect, be advised: you are plugging into the supply from hell. the main power line in an automobile is the source of a number of nasty potential transients, including load dump, reverse battery, and double battery. load dump is the result of a loose power cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse battery is just what it says, while double battery is a consequence of tow truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 9 is the most straight forward approach to protect a dc/dc converter from the ravages of an automotive power line. the series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the ltc1736 has a maximum input voltage of 36v, most applications will be limited to 30v by the mosfet bv dss . applicatio s i for atio wu u u figure 6 circuit figure 6 circuit
25 ltc1736 applicatio s i for atio wu u u design example as a design example, assume v in = 12v(nominal), v in = 22v(max), v out = 1.6v(nominal), 1.8v to 1.3v range, i max = 12a and f = 275khz. r sense and c osc can immediately be calculated: r sense = 50mv/12a = 0.0042 w c osc = 1.61(10 7 )/(275khz) C 11pf = 47pf assume a 1.2 m h inductor and check the actual value of the ripple current. the following equation is used : d i v fl v v l out out in = ? ? ? ? ()( ) 1 the highest value of the ripple current occurs at the maximum input and output voltages: d i v khz h v v a l = m ? ? ? ? = 18 275 1 2 1 18 22 5 . (. ) . the maximum ripple current is 42% of maximum output current, which is about right. next, verify the minimum on-time of 200ns is not violated. the minimum on-time occurs at maximum v in and mini- mum v out . t v vf v v khz ns on min out in max () () . () = () == 13 22 275 215 the power dissipation on the topside mosfet can be easily estimated. choosing a fairchild fds6612a results in: r ds(on) = 0.03 w , c rss = 80pf. at maximum input voltage with t(estimated) = 50 c: p v v cc v a pf khz mw main = () + [] w () + ()()( )( ) = 16 22 12 1 0 005 50 25 0 03 1 7 22 12 80 275 571 2 2 . ( . )( ) . . because the duty cycle of the bottom mosfet is much greater than the top, two larger mosfets must be paral- leled. choosing fairchild fds6680a mosfets yields a parallel r ds(on) of 0.0065 w . the total power dissipaton for both bottom mosfets, again assuming t = 50 c, is: p vv v a mw sync = ()() w () = 22 1 6 22 12 1 1 0 0065 955 2 . .. thanks to current foldback, the bottom mosfet dissipaton in short circuit will be less than under full-load conditions. c in is chosen for an rms current rating of at least 6a at temperature. c out is chosen with an esr of 0.01 w for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr ( d i l ) = 0.01 w (5a) = 50mv p-p pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1736. these items are also illustrated graphically in the layout diagram of figure 10. check the following in your layout: 1. are the signal and power grounds segregated? the ltc1736 pgnd pin should tie to the gnd plane close to the input capacitor. the sgnd pin should then connect to pgnd and all components that connect to sgnd should make a single point tie to the sgnd pin. the low side fet source pins should connect directly to the input capacitor ground. figure 9. plugging into the cigarette lighter v in 50a i pk rating 1736 f09 ltc1736 12v transient voltage suppressor general instrument 1.5ka24a
26 ltc1736 applicatio s i for atio wu u u figure 10. ltc1736 layout diagram 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 c osc run/ss i th fcb sgnd pgood sense sense + v fb v osense vid0 vid1 tg boost sw v in intv cc bg pgnd extv cc vidv cc vid4 vid3 vid2 ltc1736 1000pf 47pf c c1 c osc c c2 c ss r c + 4.7 f l1 external extv cc connection d b c in + + c b d1 m1 m2 + r sense c out + v in v out 1736 f10 sense + sense high current path 1736 f11 current sense resistor (r sense ) figure 11. kelvin sensing r sense 2. does the v osense pin connect as close as possible to the load? the optional 50pf to 100pf capacitor from v fb to sgnd should be as close as possible to the ltc1736. 3. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor be- tween sense + and sense C should be as close as possible to the ltc1736. ensure accurate current sens- ing with kelvin connections as shown in figure 11. series resistance can be added to the sense lines to increase noise rejection. 4. does the (+) terminal of c in connect to the drain of the topside mosfet(s) as closely as possible? this capaci- tor provides the ac current to the mosfet(s). 5. is the intv cc decoupling capacitor connected closely between intv cc and the power ground pin? this ca- pacitor carries the mosfet driver peak currents. an additional 1 m f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance. 6. keep the switching node (sw), top gate node (tg) and boost node (boost) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side (pins 13 to 24) of the ltc1736 and occupy minimum pc trace area.
27 ltc1736 package descriptio n u dimensions in inches (millimeters) unless otherwise noted. g package 24-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. g24 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 8.07 ?8.33* (0.318 ?0.328) 21 22 18 17 16 15 14 13 19 20 23 24 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * **
28 ltc1736 ? linear technology corporation 1999 1736f lt/tp 1299 4k ? printed in usa typical applicatio u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com 12a converter with fcb tied to pgood for cpu power; optimized for output voltages of 1.3v to 1.6v 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 c osc run/ss i th fcb sgnd pgood sense sense + v fb v osense vid0 vid1 tg boost sw v in intv cc bg pgnd extv cc vidv cc vid4 vid3 vid2 ltc1736 1000pf 47pf c c1 330pf pgood c osc 47pf c c2 47pf c ss 01. f r c 33k 100k intv cc + 4.7 f 1 f d b cmdsh-3 d1 mbrs340t3 c in 22 f/30v 2 os-con c b 0.22 f m1 fds6680a l1 1.2 h r sense 0.004 sgnd m2 fds6680a 2 output voltage programming c out : 4-180 f/4v panasonic eefueog181r (as shown) 3-470 f/6.3v kemit t51cx447m006as (alternate) 1-820 f/4v sanyo 4sp820m + 1-180 f/4v panasonic eefue0g181r (alternate) c in : sanyo os-con 305c22m l1: panasonic etqp6rz1rz0hfa 10 optional: connect to 5v 1736 ta02 + c out 180 f/4v 4 v out 1.35v to 1.6v 12a v in 4.75v to 24v + 10 related parts part number description comments ltc1147 high efficiency step-down controller 100% dc, burst mode operation, so-8 ltc1148hv/ltc1148 high efficiency synchronous step-down controllers 100% dc, burst mode operation, v in < 20v ltc1149 high efficiency synchronous step-down controller 100% dc, std threshold mosfets, v in < 48v ltc1159 high efficiency synchronous step-down controller 100% dc, logic level mosfets, v in < 40v ltc1265 1.2a monolithic high efficiency step-down switching regulator 100% dc, burst mode operation, 14-pin so lt1375/lt1376 1.5a 500khz step-down switching regulators high efficiency, constant frequency, so-8 ltc1435a high efficiency synchronous step-down controller, n-ch drive burst mode operation, 16-pin narrow so ltc1436a/ltc1436a-pll high efficiency low noise synchronous step-down converters, n-ch drive adaptive power tm mode, 20-pin/24-pin ssop ltc1474/ltc1475 ultralow quiescent current step-down monolithic switching regulators i q = 10 m a, 100% dc, 8-pin msop ltc1625/ltc1775 no r sense tm current mode synchronous step-down controllers up to 97% efficiency, burst mode operation, 16-pin ssop ltc1628 dual high efficiency 2-phase step-down controller antiphase drive, 28-pin ssop package ltc1703 550khz dual output synchronous step-down dc/dc controller 5-bit, mobile vid on output 1, no r sense ltc1735 high efficiency synchronous step-down controller, n-ch drive burst mode operation, 16-pin narrow ssop ltc1735-1 high efficiency step-down controller with power good output fault protection, 16-pin ssop and so-8 adaptive power and no r sense are trademarks of linear technology corporaton.

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